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Achieving the required performance using the lowest possible power is critical for every SoC design. Making sure the closure on performance and power are achieved in a time-frame as determined by market is key for success of a chip. However in today's SoC designs with numerous clocks and dozens of power domains, the problem is magnified many times over. With 100's of clocks and dozens of power domains, design teams take too many iterations to achieve closure, and often many companies settle for a performance lower than required, just to meet the time to market needs. 

The design and implementation of clock circuits have a direct impact on timing and power. The products, ClockExplorerTM , TimingExplorerTM and PowerExplorerTM make up a powerful design closure solution.


  • Design Closure


      • Validate CTS SDC and Constraints
      • Debug CTS results and improve timing issues


      • Reduce iterations at ECO cycle
      • Achieve faster timing convergence


      • Reduce leakage power up to 30%
      • Maintain timing QoR during power reduction


  • Lib/IP Qualification


      • Enable comprehensive qualification for Lib/IPs
      • Resolve issues in Lib/IPs with various features
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