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Published on Chip Design Magazine (Article Link)

Current Timing Closure Techniques Can’t Scale – Requires New Solution

By Dr. Jason Xing, Vice President of Engineering, ICScape Inc.

Current IC designs have advanced quickly from 65 and 45 nanometers, down to 28, 20, and below. This progression to ever-smaller geometries has brought significant challenges in achieving timing closure to meet production deadlines and market windows. Engineering teams often struggle to efficiently perform late-stage ECOs (engineering change order) to meet their design as well as time to market objectives.

In the current methodology, engineers are forced to fix ECOs using two or more different tools in the flow, iterating far too many times, often just to meet production deadlines and market windows. This method of handling ECOs will get worse with each new process node. This brings up a dire need for a solution that will allow efficient and effective handling of ECOs and hence design closure.

What are the challenges with timing closure?

  • ECO handling is a multi-tool solution and requires intimate knowledge of design, tools and process technology used.
  • Today’s designs could have several dozen design corners and many design modes, and this could generate up to 100 scenarios for timing closure.
  • Very complex timing requirements produce multiple constraints leading to a multi-objective timing ECO process.
  • Today’s chip density and the complexity of routing makes late routing changes a real challenge.
  • Multiple power domains are very common today. This creates the need for specific buffers to be placed on routes that traverse alternate power domains, which further complicates routing.
  • Correlation issues stemming from the difference between the timing engines that are part of the STA tool and the place and route tool in a typical ECO flow.
  • Lack of physical awareness of signoff STA tool adds to the correlation issue.

Current methodology uses STA and place and route tools (each with their own timing engine) as a minimal set to address the ECO problem. Often an ECO tool comes into the picture as well. Such a multi-tool solution suffers from correlation-related problems, forcing many additional iterations to achieve closure – often ten or more passes through the flow.

Two factors that affect correlation between the tools in the current methodology are timing and layout considerations. Today, an ECO tool typically works with incomplete information such as a timing violation report or partial timing graphs. Solutions created using such incomplete information often fix one problem but introduce others. When the ECO tool uses its own timing engine, it is almost impossible to match the results of the original STA tool.

Layout considerations are another factor that must be accounted for in the ECO process. ECO changes based on the netlist alone with no understanding of the physical constraints of the current design will lead to unpredictable layout changes due to cell legalization or ECO routing constraints. While each such ECO iteration fixes some violations, it also introduces new violations, resulting in many more iterations to fix all violations. This leads to longer time for design closure.

So how do we solve this impending timing ECO problem? I see three approaches. The most common approach is the creation and application of a script by the user. This is typically based on estimated delays computed using incomplete data from a violation report or partial STA graphs, and easy ways to fix timing violations, without taking the challenges of the “current” layout into consideration. This approach suffers from both timing engine and layout correlation issues.

The second type of ECO solution is an optimizer on top of the STA tool. Since the STA engine does not use physical information, this method suffers from lack of layout correlation.

The third type of tool is built upon place and route software. This approach accounts for the layout, but since it must perform its own timing calculation, it still has trouble matching the STA engine. Often large timing margins are used to compensate for this lack of correlation with the STA engine, leading to insertion of too many buffers, increasing routing congestion and power consumption. Furthermore, the performance of a place and route tool will slow down considerably when there is more than a couple of scenarios to be considered simultaneously.

What’s required is an ECO solution that concurrently handles timing and layout considerations, taking into account a design’s complete timing information from the signoff STA engine and current state of its layout to optimize and achieve faster timing closure, using fewer iterations and smaller buffer count.


Jason Xing is co-founder and Vice President of Engineering at ICScape, where he architected the timing, clock and power closure products. Jason has over 15 years EDA research and development experience. In 1997, He joined Sun Labs after receiving his PhD in Computer Science from the University of Illinois at Urbana-Champaign. At Sun Labs, Xing did research on physical and logical concurrent design methodologies and shape-based routing technologies. In 2001, he joined the Sun Microsystems internal CAD development team before he started ICScape in 2005. Jason holds another PhD in Mathematics from University of Louisiana.



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